Inventive concepts relate to a voltage-controlled delay line used to generate a plurality of clock signals, and more particularly, to a voltage-controlled delay line that stably operates even at the initial stage of power supply and has the same delay value between a plurality of generated clock signals.
A delay-locked loop circuit is used in a synchronous semiconductor memory device to control a time point at which data is output from the synchronous semiconductor device by using an external clock signal. Clock signals having different delay components, that is, multi-phase clock signals, are used to reproduce data written to an optical disk or the like. That is, when an optical disk reproducing apparatus performs tracking on an optical disk, multi-phase clock signals are used to detect a tracking error. Each of the delay-locked loop circuit and the optical disk reproducing apparatus used in the synchronous semiconductor memory device includes a voltage-controlled delay line for generating a plurality of delay clock signals that are obtained by delaying an input clock signal by a predetermined period of time.